CMOS technology has evolved such that the computer market has rapidly opened to a wide range of consumers. Today multi-media requires at least a 64 MB, and preferably even a 128 MB memory, which increases the relative cost of the memory system within the computer. In the near future, it is likely that 256 MB and 512 MB computers will become commonplace, which suggests a potential strong demand for 256 Mb DRAMs (Dynamic Random Access Memory) and beyond. Still in the development stage, DRAMs in the Gigabit range are already under way. As DRAM density and lithographic difficulties increase, it is more difficult to have a fully functional DRAMs. This necessitates the introduction of new techniques that guarantee a reasonable chip yield notwithstanding the added complexity of the design and manufacture of such memory devices. Process and design engineers are continuously attempting to reduce and, ultimately, eliminate mask defects. Faults that inevitably remain in the chip are generally overcome using special circuit designs, and, more specifically, redundancy replacement.
A conventional redundancy replacement architecture of a memory is shown in FIG. 1. Memory chip (100) includes a plurality of elements (112) in at least one array (110) supported by a plurality of decoders (120) that select a corresponding element (112) with the address inputs (ADDs). The element is selected when the STROBE signal switches to high, activating the element (112) by way of a corresponding decoder (122). In order to implement a redundancy replacement architecture, array (110) additionally includes at least one redundancy element (RE 114). More particularly, RE (114) replaces the element (112) having the fault (labeled X) with the selection of the switch being controlled by a redundancy circuit (130). Redundancy circuit (130) includes a plurality of laser fuses (132) that identify the (redundancy) addresses of the corresponding faulty elements, and generate a redundancy match detection signal (RMD). In order to program this address, selected laser fuses are blown at wafer level before the chip is mounted on the next level of packaging, e.g., a multi-chip module. Thus, when the input addresses (ADDs) match the programed redundancy address, the signal RMD shifts to a high. Moreover, in order not to activate the element (112) having a fault when STROBE switches to high, the decoder (122) requires to be disabled. The high state of RMD, on the other hand, enables redundancy decoder (124) to activate RE (114) when STROBE switches to high. This redundancy replacement method effectively overcomes the functionality problem even in the presence of a defective element at wafer level. However, any further defects occurring subsequently up to and including the final packaging of the chip are not repaired, because further of redundancy addresses by laser is no longer possible at module level. This results in a yield loss.
It is known in the art that electrically programmable fuses (e-fuses) make it possible to blow fuses electrically, an ideal solution for module level redundancy. FIG. 2 shows a typical redundancy circuit (130) provided with e-fuses. Redundancy circuit (130) consists of an e-fuse block (220) and a redundancy match detection decoder (210). The e-fuse block (220) consists of a plurality of e-fuses (222) and e-fuse decoders (224). The e-fuses (222) are programmed to identify redundancy addresses of the faulty elements, analogous to the laser programmable fuses. Unlike the laser programmable fuses, e-fuses (222) are blown by applying a large voltage to the fuse selected. The e-fuse decoders (224) interpret the address inputs (ADDs) and determine which e-fuse (222) are to be programmed. The example shown in FIG. 2 illustrates how e-fuse decoder (224-A) selects e-fuse (222-A) by opening a corresponding NMOS (226-A). As a result, a large current (I) flows from the high voltage supply (VSOURCE) to ground through the selected e-fuse (222-A) when the VSOURCE switches to high. The high voltage is typically supplied from the high voltage generator (230). The power (P) applied to the e-fuse with resistance (R) is determined by P=I.sup.2 R. If P is sufficiently large at a given spot of the e-fuse, the e-fuse conductivity is severed. This process is repeated for blowing other e-fuses to identify the redundancy addresses.